jonaskruckenberg.de
Next Generation WASM Microkernel Operating System
chore: allow riscv crate to be compiled on non-riscv architectures
+11
-7
+4
libs/riscv/src/lib.rs
+4
libs/riscv/src/lib.rs
+7
-7
libs/riscv/src/register/satp.rs
+7
-7
libs/riscv/src/register/satp.rs
···
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}
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}
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impl Satp {
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-
#[cfg(target_arch = "riscv32")]
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+
#[cfg(target_pointer_width = "32")]
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pub fn ppn(&self) -> usize {
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self.bits & 0x3f_ffff // bits 0-21
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}
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-
#[cfg(target_arch = "riscv64")]
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+
#[cfg(target_pointer_width = "64")]
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#[must_use]
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pub fn ppn(&self) -> usize {
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self.bits & 0xfff_ffff_ffff // bits 0-43
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}
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-
#[cfg(target_arch = "riscv32")]
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+
#[cfg(target_pointer_width = "32")]
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pub fn asid(&self) -> usize {
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(self.bits >> 22) & 0x1ff // bits 22-30
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}
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-
#[cfg(target_arch = "riscv64")]
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+
#[cfg(target_pointer_width = "64")]
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#[must_use]
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pub fn asid(&self) -> u16 {
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// Safety: `& 0xffff` ensures the number must be 16 bit
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unsafe { u16::try_from((self.bits >> 44) & 0xffff).unwrap_unchecked() } // bits 44-60
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}
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-
#[cfg(target_arch = "riscv32")]
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+
#[cfg(target_pointer_width = "32")]
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pub fn mode(&self) -> Mode {
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match (self.bits >> 31) != 0 {
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true => Mode::Sv32,
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false => Mode::Bare,
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}
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}
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-
#[cfg(target_arch = "riscv64")]
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+
#[cfg(target_pointer_width = "64")]
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#[must_use]
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pub fn mode(&self) -> Mode {
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// bits 60-64
···
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Sv64 = 11,
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}
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-
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
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+
#[cfg(any(target_pointer_width = "32", target_pointer_width = "64"))]
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impl fmt::Debug for Satp {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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f.debug_struct("Satp")